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INFO [wishbone_tool::bridge::ethernet] Re-opened ethernet host 10.188.0.220:1234

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2020 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Apr  2 2020 23:20:05
 BIOS CRC passed (2ab71a26)

 Migen git sha1: 3f9809b
 LiteX git sha1: 27f00851

--=============== SoC ==================--
CPU:       VexRiscv @ 125MHz
ROM:       32KB
SRAM:      4KB
L2:        8KB
MAIN-RAM:  4096KB

--=========tion ============--
Initializing SDRAM...
SDRAM now under hardware control
Memtest bus failed: 192/256 errors
192/256 errorsailed: 524288/524288 errors
Memtest addr failed: 8192/8192 errors
Memory initialization failed

--============= Console ================--
litex>