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jul 10/04:53:10.834 DEBUG2 : 		

StartSession()

jul 10/04:53:10.834 INFO   : Debug Log(info): Loading the CMSIS-DAP driver
jul 10/04:53:10.834 DEBUG2 : 		-> ConnectToHardware()
jul 10/04:53:10.834 DEBUG2 : 		-> CreateJetTerminal()
jul 10/04:53:10.834 DEBUG2 : 		<- CreateJetTerminal()
jul 10/04:53:10.834 DEBUG2 : 		-> AcquireSigAPIPtr()
jul 10/04:53:10.834 DEBUG2 : 		  SigAPISetPath('C:\Program Files\IAR Systems\Embedded Workbench 9.2\arm\bin\jet\bin')
jul 10/04:53:10.838 DEBUG2 : 		<- AcquireSigAPIPtr()
jul 10/04:53:10.838 DEBUG2 : 		-> CreateSigProbe()
jul 10/04:53:10.838 DEBUG2 : 		  SigProbe version: 1.24
jul 10/04:53:10.838 DEBUG2 : 		<- CreateSigProbe()
jul 10/04:53:10.838 DEBUG2 : 		-> SigProbeInit()
jul 10/04:53:10.838 DEBUG2 : 		<- SigProbeInit()
jul 10/04:53:10.838 INFO   : Debug Log(info): Probe: CMSIS-DAP probe SW module ver 1.24

jul 10/04:53:10.838 INFO   : Probe: CMSIS-DAP probe SW module ver 1.24

jul 10/04:53:10.838 DEBUG2 : 		-> ConnectToProbe()
jul 10/04:53:10.838 DEBUG2 : 		  ISigProbe::EnumScan()
jul 10/04:53:10.842 DEBUG2 : 		  scanning finished: found 1 probes
jul 10/04:53:10.847 DEBUG2 : 		    connection Serial No: CMSIS-DAP v1:2FCC8092A2189006
jul 10/04:53:10.851 DEBUG2 : 		    connection found probes: 
jul 10/04:53:10.855 INFO   : Debug Log(info): Probe: Connecting to CMSIS-DAP v1:2FCC8092A2189006 firmware v.2.1.0

jul 10/04:53:10.855 INFO   : Probe: Connecting to CMSIS-DAP v1:2FCC8092A2189006 firmware v.2.1.0

jul 10/04:53:10.855 DEBUG2 : 		<- ConnectToProbe()
jul 10/04:53:10.855 DEBUG2 : 		-> CreateSigEmus()
jul 10/04:53:10.855 DEBUG2 : 		  ISigAPI::CreateInstance('ISigEmu', 'EARM', '')
jul 10/04:53:10.859 DEBUG2 : 		Core 0: sigEmu->LinkAttach(ISigProbe)
jul 10/04:53:10.859 DEBUG2 : 		  core 0: IsigEmu::ParamSet('Emulator', 'cmsisdap')
jul 10/04:53:10.859 DEBUG2 : 		  core 0: IsigEmu::ParamSet('Processor', 'Cortex-M7')
jul 10/04:53:10.859 DEBUG2 : 		  core 0: IsigEmu::ParamSet('JtagHeader', 'ARM-SWD')
jul 10/04:53:10.859 DEBUG2 : 		  core 0: IsigEmu::ParamSet('CoreSightSWJ', 'SWD')
jul 10/04:53:10.859 DEBUG2 : 		  core 0: IsigEmu::ParamSet('JTagSpeed', '25000')
jul 10/04:53:10.859 DEBUG2 : 		  core 0: IsigEmu::ParamSet('BoardCfg', '-auto')
jul 10/04:53:10.859 DEBUG2 : 		  core 0: IsigEmu::ParamSet('JtagInitDelay', '200,r:300')
jul 10/04:53:10.859 DEBUG2 : 		  core 0: IsigEmu::ParamSet('BigEndian', '0')
jul 10/04:53:10.859 DEBUG2 : 		  ISigEmu::LinkAttach('SigTerminalLog'...)
jul 10/04:53:10.859 DEBUG2 : 		Core 0: sigEmu->LinkAttach(SigTerminalLog)
jul 10/04:53:10.859 DEBUG2 : 		<- CreateSigEmus()
jul 10/04:53:10.859 DEBUG2 : 		-> CreateInterfaceComProtocol()
jul 10/04:53:10.859 DEBUG2 : 		  ISigProbe::AcquireInterface('ComProtocol')
jul 10/04:53:10.859 DEBUG2 : 		<- CreateInterfaceComProtocol()
jul 10/04:53:10.859 DEBUG2 : 		-> CollectCoreNames()
jul 10/04:53:10.859 DEBUG2 : 		<- CollectCoreNames()
jul 10/04:53:10.859 DEBUG2 : 		-> DoIceConnect()
jul 10/04:53:10.859 DEBUG2 : 		  core 0: IsigEmu::ParamSet('BoardDID', '')
jul 10/04:53:10.859 DEBUG2 : 		Core 0: IceConnect(...)
jul 10/04:53:10.860 DEBUG2 : 		<- DoIceConnect()
jul 10/04:53:10.860 DEBUG2 : 		-> DoIceInit()
jul 10/04:53:10.860 DEBUG2 : 		Core 0: IceInit(...)
jul 10/04:53:10.863 DEBUG2 : 		ISigEmu::IceVersion(209)
jul 10/04:53:10.863 INFO   : Debug Log(info): Emulation layer version 5.21
jul 10/04:53:10.863 DEBUG2 : 		ISigEmu::IceStatus(0)
jul 10/04:53:10.863 DEBUG2 : 		<- DoIceInit()
jul 10/04:53:10.863 DEBUG2 : 		-> CreateCmdInterpreter()
jul 10/04:53:10.863 DEBUG2 : 		  ISigProbe::CreateInstance(..., 'SigCmdInterpreter', '')
jul 10/04:53:10.863 DEBUG2 : 		<- CreateCmdInterpreter()
jul 10/04:53:10.863 DEBUG2 : 		  ISigCmdInterpreter::LinkAttach('ISigEmu',...)
jul 10/04:53:10.863 DEBUG2 : 		-> AcquireA2DInterface()
jul 10/04:53:10.863 DEBUG2 : 		  ISigProbe::AcquireInterface('ISigA2D')
jul 10/04:53:10.863 ERROR  :   ConnectToHardware(): Failed to create sigA2D object
jul 10/04:53:10.867 INFO   : Debug Log(info): Notification to core-connect hookup.

jul 10/04:53:10.867 INFO   : Notification to core-connect hookup.

jul 10/04:53:10.867 DEBUG2 : 		<Call to _ExecDeviceCoreConnect: macro undefined
jul 10/04:53:10.867 DEBUG2 : 		<Call to execUserCoreConnect: macro undefined
jul 10/04:53:10.868 INFO   : Debug Log(info): Connected DAP v2 on SWD. Detected DP ID=0x5ba02477.

jul 10/04:53:10.868 INFO   : Connected DAP v2 on SWD. Detected DP ID=0x5ba02477.

jul 10/04:53:11.002 INFO   : Debug Log(info): Connecting to TAP#0 DAP AHB-AP port 0x0 (IDR=0x7477'0001).

jul 10/04:53:11.002 INFO   : Connecting to TAP#0 DAP AHB-AP port 0x0 (IDR=0x7477'0001).

jul 10/04:53:11.002 INFO   : Debug Log(info): Recognized CPUID=0x411fc271 Cortex-M7 r1p1 arch ARMv7-M

jul 10/04:53:11.002 INFO   : Recognized CPUID=0x411fc271 Cortex-M7 r1p1 arch ARMv7-M

jul 10/04:53:11.006 INFO   : Debug Log(info): Set cacheable access on AHB-AP port 0 (HPROT=0xeb000000).

jul 10/04:53:11.006 INFO   : Set cacheable access on AHB-AP port 0 (HPROT=0xeb000000).

jul 10/04:53:11.010 INFO   : Debug Log(info): Debug resources: 8 instruction comparators, 4 data watchpoints.

jul 10/04:53:11.010 INFO   : Debug resources: 8 instruction comparators, 4 data watchpoints.

jul 10/04:53:11.034 DEBUG2 : 		  ConnectToHardware(), checking status (#1): Core 0: CpuStatus(status = <0x1: CPU_STATUS_MPOWER>) = 0
jul 10/04:53:11.034 INFO   : Debug Log(minor): CPU status OK
jul 10/04:53:11.034 DEBUG2 : 		<- AcquireA2DInterface()
jul 10/04:53:11.034 DEBUG2 : 		-> AcquireEmuVectInterface()
jul 10/04:53:11.034 DEBUG2 : 		  ISigEmu::AcquireInterface('ISigEmuVect') (core 0)
jul 10/04:53:11.034 DEBUG2 : 		<- AcquireEmuVectInterface()
jul 10/04:53:11.034 DEBUG2 : 		-> AcquireEmuWptInterface()
jul 10/04:53:11.034 DEBUG2 : 		  ISigEmu::AcquireInterface('ISigEmuWpt')
jul 10/04:53:11.038 DEBUG2 : 		<- AcquireEmuWptInterface()
jul 10/04:53:11.038 DEBUG2 : 		-> AcquirePcSamplerInterface()
jul 10/04:53:11.038 DEBUG2 : 		  ISigEmu::AcquireInterface('ISigPcSampler')
jul 10/04:53:11.039 DEBUG2 : 		<- AcquirePcSamplerInterface()
jul 10/04:53:11.039 DEBUG2 : 		<- ConnectToHardware()
jul 10/04:53:11.039 DEBUG2 : 		StartSession() checking powerCore 0: CpuStatus(status = <0x1: CPU_STATUS_MPOWER>) = 0
jul 10/04:53:11.039 DEBUG2 : 		Core 0: IceInfo(0, ...)
jul 10/04:53:11.054 INFO   : Debug Log(info): Loaded debugee: C:\Users\x2tal\Documents\vegard\foo\Debug\Exe\foo.out
jul 10/04:53:11.072 DEBUG2 : 		StopDownload()
jul 10/04:53:11.075 DEBUG2 : 		VectorCatchGet(core 0, allowed mask 0xff, current mask 0x0)
jul 10/04:53:11.075 DEBUG2 : 		VectorCatchSet(core 0, mask 0x1fe)
jul 10/04:53:11.081 INFO   : Debug Log(info): Attach to running target completed.
jul 10/04:53:11.081 DEBUG2 : 		============== Finished loading application. Now online.
jul 10/04:53:11.092 DEBUG2 : 		CpuRegGet(Core 0, PC -> 15) = 0xfffffffe (4294967294)
jul 10/04:53:11.094 DEBUG2 : 		SetCodeBreak(<0:0x62>, 1 units, 'Stack window trigger')
jul 10/04:53:11.094 DEBUG2 : 		  SetCodeBreak(): BreakSetAttr(bank 0, count 1, addr 0x62, attr <0x20009: CPUMODE(THUMB) | SIGEMU_BRK_ATTR_SET | SIGEMU_BRK_ATTR_HW>)
jul 10/04:53:11.094 DEBUG2 : 		  SetBreakpoint(): BreakGetAttr(bank 0, count 1, addr 0x62, attr <0x20409: CPUMODE(THUMB) | SIGEMU_BRK_ATTR_SET | SIGEMU_BRK_ATTR_HW | SIGEMU_BRK_ATTR_LITTLEENDIAN>)
jul 10/04:53:11.094 DEBUG2 : 		-> SetupTrace()
jul 10/04:53:11.094 DEBUG2 : 		-> AcquireXTrace()
jul 10/04:53:11.094 DEBUG2 : 		  ISigProbe::AcquireInterface('ISigXTrace')
jul 10/04:53:11.094 DEBUG2 : 		  ISigAPI::CreateInstance('ISigXTrace')
jul 10/04:53:11.096 DEBUG2 : 		<- AcquireXTrace()
jul 10/04:53:11.096 DEBUG2 : 		  ISigXTrace::LinkAttach('SigTerminalLog',...)
jul 10/04:53:11.096 DEBUG2 : 		  ISigXTrace::LinkAttach('ISigXTraceClient',...)
jul 10/04:53:11.096 DEBUG2 : 		  ISigXTrace::LinkAttach('SigEmu',...)
jul 10/04:53:11.096 DEBUG2 : 		  ISigXTrace::LinkAttach('SigProbe',...)
jul 10/04:53:11.096 DEBUG2 : 		-> SetupLowLevelTrace()
jul 10/04:53:11.096 DEBUG2 : 		  ISigXTrace::Init('SWO,ETB')
jul 10/04:53:11.098 INFO   : Debug Log(info): INFO: Configuring trace using 'SWO,ETB' setting...

jul 10/04:53:11.098 INFO   : INFO: Configuring trace using 'SWO,ETB' setting...

jul 10/04:53:11.104 INFO   : Debug Log(info): Trace: Using ETMv4 at address 0xe0041000

jul 10/04:53:11.104 INFO   : Trace: Using ETMv4 at address 0xe0041000

jul 10/04:53:11.108 INFO   : Debug Log(info): Trace: ETMv4 is already powered-up (TRCPDSR=0x1)

jul 10/04:53:11.108 INFO   : Trace: ETMv4 is already powered-up (TRCPDSR=0x1)

jul 10/04:53:11.114 INFO   : Debug Log(info): INFO: SWO trace mode is not supported by the probe (use I-jet/I-jet-Trace probe) - trace is disabled.

jul 10/04:53:11.114 INFO   : INFO: SWO trace mode is not supported by the probe (use I-jet/I-jet-Trace probe) - trace is disabled.

jul 10/04:53:11.114 DEBUG2 : 		  ISigXTrace::TraceInfo(...) -> NULL (no trace)
jul 10/04:53:11.114 DEBUG2 : 		  ISigAPI::ReleaseInstance(sigXTrace)
jul 10/04:53:11.114 DEBUG2 : 		<- SetupLowLevelTrace()
jul 10/04:53:11.114 DEBUG2 : 		-> AcquireSWOInterface()
jul 10/04:53:11.114 DEBUG2 : 		  ISigProbe::AcquireInterface('ISigSWO')
jul 10/04:53:11.114 ERROR  :   ConnectToHardware(): Failed to create sigSWO object.
jul 10/04:53:11.114 DEBUG2 : 		<- AcquireSWOInterface()
jul 10/04:53:11.114 DEBUG2 : 		-> CreateSigChanInterface()
jul 10/04:53:11.114 DEBUG2 : 		<- CreateSigChanInterface()
jul 10/04:53:11.114 DEBUG2 : 		-> SetupSigChanInterface()
jul 10/04:53:11.114 DEBUG2 : 		<- SetupSigChanInterface()
jul 10/04:53:11.117 DEBUG2 : 		<- SetupTrace()
jul 10/04:53:11.117 DEBUG2 : 		-> SetupProfiling()
jul 10/04:53:11.117 DEBUG2 : 		<- SetupProfiling()
jul 10/04:53:11.117 DEBUG2 : 		<Call to _ExecDeviceAttach: macro undefined
jul 10/04:53:11.117 DEBUG2 : 		<Call to execUserAttach: macro undefined
jul 10/04:53:11.117 DEBUG2 : 		SetCodeBreak(<9:0xf000000000000000>, 1 units, 'C-SPY Terminal I/O && library support module')
jul 10/04:53:11.139 DEBUG2 : 		PlDriver::Go(core 0): mIsExecuting[0] = true
jul 10/04:53:11.139 DEBUG2 : 		-> LowLevelGo(core 0)
jul 10/04:53:11.139 DEBUG2 : 		CpuRegGet(Core 0, PC ->15) = 0xfffffffe (4294967294)
jul 10/04:53:11.141 DEBUG2 : 		  ReadPostCache(): MemRead(core 0, 0:0xfffffffe, 2 bytes [by 2] = [ 00 00 ])
jul 10/04:53:11.141 ERROR  : MemRead() returned Failure while executing the operation ;   ReadPostCache(): 
jul 10/04:53:11.141 DEBUG2 : 		<Call to _ExecDeviceExecutionStarted: macro undefined
jul 10/04:53:11.141 DEBUG2 : 		<Call to execUserExecutionStarted: macro undefined
jul 10/04:53:11.141 DEBUG2 : 		  LowLevelGo(core 0) [multi = false], CpuStatus(): Core 0: CpuStatus(status = <0x1: CPU_STATUS_MPOWER>) = 0
jul 10/04:53:11.141 DEBUG2 : 		Core 0:   LowLevelGo(core 0) [multi = false], CpuGo()
jul 10/04:53:11.170 INFO   : Debug Log(info): CPU status - LOCKUP
jul 10/04:54:51.266 DEBUG2 : 		LowLevelStop(0): mStoppedByLowLevelStop[0] = true
jul 10/04:54:51.281 DEBUG2 : 		LowLevelGo(core 0): Stop requested by stop flag
jul 10/04:54:51.281 DEBUG2 : 		Core 0: LowLevelGo(core 0) [multi = false]: ISigEmu::CpuStop()
jul 10/04:54:51.281 DEBUG2 : 		-> WaitForCpuToStop(core 0)
jul 10/04:54:51.297 DEBUG2 : 		LowLevelGo(core 0): Core 0: CpuStatus(status = <0x1: CPU_STATUS_MPOWER>) = 0
jul 10/04:54:51.297 INFO   : Debug Log(minor): CPU status OK
jul 10/04:54:51.297 DEBUG2 : 		<- WaitForCpuToStop(core 0)
jul 10/04:54:51.297 DEBUG2 : 		LowLevelGo(core 0): WaitForCpuToStop(0) returned waitRes = 0
jul 10/04:54:51.298 DEBUG2 : 		LowLevelGo(core 0): Setting single mIsExecuting[0] = false [multi == false]
jul 10/04:54:51.298 DEBUG2 : 		LowLevelGo(core 0): CPU core 0 is now stopped, after 7569 polls in 100.111s
jul 10/04:54:51.298 DEBUG2 : 		<Call to _ExecDeviceExecutionStopped: macro undefined
jul 10/04:54:51.298 DEBUG2 : 		<Call to execUserExecutionStopped: macro undefined
jul 10/04:54:51.298 DEBUG2 : 		CpuRegGet(Core 0, PC -> 15) = 0xfffffffe (4294967294)
jul 10/04:54:51.298 DEBUG2 : 		  ReadPostCache(): MemRead(core 0, 0:0xfffffffe, 2 bytes [by 2] = [ f0 d1 ])
jul 10/04:54:51.298 ERROR  : MemRead() returned Failure while executing the operation ;   ReadPostCache(): 
jul 10/04:54:51.300 DEBUG2 : 		LowLevelGo(core 0): Stopped at breakpoint
jul 10/04:54:51.300 DEBUG2 : 		<- LowLevelGo(core 0)
jul 10/04:54:51.300 DEBUG2 : 		PlDriver::Go(core 0): goStatus = 1
jul 10/04:54:51.301 DEBUG2 : 		ISigPcSampler::GetSample(SIGAPIARM_SAMPLE_CYCLE) = 0x131ae1f6
jul 10/04:54:51.302 DEBUG2 : 		CpuRegGet(Core 0, LR -> 14) = 0xfffffff9 (4294967289)
jul 10/04:54:51.302 DEBUG2 : 		CpuRegGet(Core 0, XPSR -> 16) = 0x1000003 (16777219)
jul 10/04:54:51.303 DEBUG2 : 		  ReadPostCache(): MemRead(core 0, 0:0xe000e008, 4 bytes [by 4] = [ 00 10 00 00 ])
jul 10/04:54:51.304 DEBUG2 : 		  ReadPostCache(): MemRead(core 0, 0:0xe000ed24, 4 bytes [by 4] = [ 00 00 00 00 ])
jul 10/04:54:51.304 DEBUG2 : 		  ReadPostCache(): MemRead(core 0, 0:0xe000ed28, 3 bytes [by 0] = [ 01 04 00 ])
jul 10/04:54:51.306 DEBUG2 : 		  ReadPostCache(): MemRead(core 0, 0:0xe000ed2b, 4 bytes [by 4] = [ 00 00 00 00 ])
jul 10/04:54:51.308 DEBUG2 : 		  ReadPostCache(): MemRead(core 0, 0:0xe000ed2f, 4 bytes [by 4] = [ 40 00 00 00 ])
jul 10/04:54:51.309 DEBUG2 : 		  ReadPostCache(): MemRead(core 0, 0:0xe000ed33, 7 bytes [by 0] = [ 00 00 00 00 00 00 00 ])
jul 10/04:54:51.310 DEBUG2 : 		  ReadPostCache(): MemRead(core 0, 0:0xe000ed3a, 4 bytes [by 4] = [ 00 00 00 00 ])
jul 10/04:54:51.310 DEBUG2 : 		  ReadPostCache(): MemRead(core 0, 0:0xe000ed3e, 4 bytes [by 4] = [ 00 00 30 00 ])
jul 10/04:54:51.313 DEBUG2 : 		CpuRegGet(Core 0, SP_Main -> 17) = 0xffffffd8 (4294967256)
jul 10/04:54:51.313 INFO   : Debug Log(info): HardFault exception.
The processor has escalated a configurable-priority exception to HardFault.

   An MPU or Execute Never (XN) default memory map access violation has occurred on an instruction fetch (CFSR.IACCVIOL, MMFAR).

   An imprecise data access error has occurred (CFSR.IMPRECISERR, BFAR).

Could not determine the location where the exception occurred.

See the call stack for more information.

jul 10/04:54:51.367 DEBUG2 : 		-> AboutToStopSession()
jul 10/04:54:51.369 DEBUG2 : 		<- AboutToStopSession()
jul 10/04:54:51.369 DEBUG2 : 		<Call to _ExecDeviceExit: macro undefined
jul 10/04:54:51.369 DEBUG2 : 		<Call to execUserExit: macro undefined
jul 10/04:54:51.379 DEBUG2 : 		ClearCodeBreak(<0:0x62>, 1 units)
jul 10/04:54:51.379 DEBUG2 : 		  ClearCodeBreak(): BreakClr(bank 0, count 1, addr 0x62)
jul 10/04:54:51.403 DEBUG2 : 		-> PrepareStopSession()
jul 10/04:54:51.403 DEBUG2 : 		<- PrepareStopSession()
jul 10/04:54:51.447 DEBUG2 : 		ClearCodeBreak(<9:0xf000000000000000>, 1 units)
jul 10/04:54:51.451 DEBUG2 : 		StopGui()
jul 10/04:54:51.500 DEBUG2 : 		-> StopSession()
jul 10/04:54:51.556 DEBUG2 : 		-> TerminateHardware()
jul 10/04:54:51.556 DEBUG2 : 		  ISigEmu::ReleaseInterface(pcSampler)
jul 10/04:54:51.556 DEBUG2 : 		  ISigEmu::ReleaseInterface(sigWpt)
jul 10/04:54:51.556 DEBUG2 : 		  ISigEmu::ReleaseInterface(sigVect)
jul 10/04:54:51.556 DEBUG2 : 		  ISigEmu::IceTerm()
jul 10/04:54:51.560 DEBUG2 : 		Core 0: sigEmu->LinkAttach(ISigProbe)
jul 10/04:54:51.560 DEBUG2 : 		  ISigApi::ReleaseInstance(sigEmu)
jul 10/04:54:51.560 DEBUG2 : 		  SigAPITerm()
jul 10/04:54:51.560 DEBUG2 : 		<- TerminateHardware()
jul 10/04:54:51.560 DEBUG2 : 		<- StopSession()
jul 10/04:54:51.560 DEBUG2 : 		-> ~TdJetDriver()
jul 10/04:54:51.560 DEBUG2 : 		-> TerminateHardware()
jul 10/04:54:51.560 DEBUG2 : 		<- TerminateHardware()