diff --git a/liteeth/core/arp.py b/liteeth/core/arp.py index c272718..d885af3 100644 --- a/liteeth/core/arp.py +++ b/liteeth/core/arp.py @@ -53,7 +53,7 @@ class LiteEthARPTX(Module): ) self.comb += [ packetizer.sink.last.eq(counter == (packet_words - 1)), - packetizer.sink.last_be.eq(1 if len(packetizer.sink.last_be) == 1 else 2**(packet_length%(dw//8)-1)), + packetizer.sink.last_be.eq(1 if len(packetizer.sink.last_be) == 1 else 2**((packet_length-1)%(dw//8))), packetizer.sink.hwtype.eq(arp_hwtype_ethernet), packetizer.sink.proto.eq(arp_proto_ip), packetizer.sink.hwsize.eq(6), diff --git a/liteeth/frontend/etherbone.py b/liteeth/frontend/etherbone.py index 5c3b548..efc761a 100644 --- a/liteeth/frontend/etherbone.py +++ b/liteeth/frontend/etherbone.py @@ -335,7 +335,7 @@ class LiteEthEtherboneRecord(Module): sink.connect(depacketizer.sink), depacketizer.source.connect(receiver.sink) ] - if endianness is "big": + if endianness == "big": self.comb += receiver.sink.data.eq(reverse_bytes(depacketizer.source.data)) # Save last ip address @@ -361,7 +361,7 @@ class LiteEthEtherboneRecord(Module): (sender.source.rcount != 0)*4 + sender.source.rcount*4), source.ip_address.eq(last_ip_address) ] - if endianness is "big": + if endianness == "big": self.comb += packetizer.sink.data.eq(reverse_bytes(sender.source.data)) # Etherbone Wishbone Master ------------------------------------------------------------------------ diff --git a/liteeth/phy/ecp5rgmii.py b/liteeth/phy/ecp5rgmii.py index 2b529d2..aeda5da 100644 --- a/liteeth/phy/ecp5rgmii.py +++ b/liteeth/phy/ecp5rgmii.py @@ -62,7 +62,7 @@ class LiteEthPHYRGMIIRX(Module, AutoCSR): ("``0b0``", "Link down."), ("``0b1``", "Link up."), ]), - CSRField("clock_speed", size=1, values=[ + CSRField("clock_speed", size=2, values=[ ("``0b00``", "2.5MHz (10Mbps)."), ("``0b01``", "25MHz (100MBps)."), ("``0b10``", "125MHz (1000MBps)."),