| INFO:SoC:Converting MEM data width: 128 to 64 via Wishbone
Traceback (most recent call last):
File "./acorn_cle_215.py", line 216, in <module>
main()
File "./acorn_cle_215.py", line 200, in main
soc = PCIeSoC(platform, **soc_sdram_argdict(args))
File "./acorn_cle_215.py", line 128, in __init__
l2_cache_reverse = True
File "/home/zyp/fpga_sandbox/litex/litex/soc/integration/soc.py", line 1103, in add_sdram
self.submodules += wishbone.Converter(mem_wb, litedram_wb)
File "/home/zyp/fpga_sandbox/litex/litex/soc/interconnect/wishbone.py", line 298, in __init__
raise NotImplementedError
NotImplementedError
|